例句與造句

1. Both architectures define branch delay slots in order to utilize these fetched instructions.
2. Many early RISC designs also shared the characteristic of having a branch delay slot.
3. A branch delay slot is an instruction space immediately following a jump or branch.
4. Another technique is a branch delay slot.
5. The goal of a breakpoints on instructions as well as stepping while debugging within branch delay slot.
6. It's difficult to find branch delay slot in a sentence. 用branch delay slot造句挺難的
7. RISC-V omits a branch delay slot because it complicates multicycle CPUs, superscalar CPUs, and long pipelines.
8. Because they use branch delay slots, fetched just one instruction per cycle, and execute in-order, there is no performance loss.
9. The compilers were designed to keep the processors as full as possible by reducing the number of branch delay slots, and did a particularly good job of it.
10. Many RISC designs have included a branch delay slot, a position after a branch instruction that can be filled with an instruction which is executed whether or not the branch is taken.
11. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it ( such as PowerPC and more recent versions of SPARC and MIPS ).
12. The ideal number of branch delay slots in a particular pipeline implementation is dictated by the number of pipeline stages, the presence of register forwarding, what stage of the pipeline the branch conditions are computed, whether or not a branch target buffer ( BTB ) is used and many other factors.
13. This makes conditional branches a problem, because the compiler has to fill the instruction following a conditional branch ( the so-called " branch delay slot " ), with something selected to be " safe " ( i . e ., not dependent on the outcome of the conditional ).